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NXP Semiconductors /LPC18xx /SDMMC /CLKSRC

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Interpret as CLKSRC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CLK_SOURCE 0RESERVED

Description

SD Clock Source Register

Fields

CLK_SOURCE

Clock divider source for SD card. 00 - Clock divider 0 01 - Clock divider 1 10 - Clock divider 2 11 - Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented.
RESERVED

Reserved

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data